The present invention relates to a semiconductor memory and, more particularly, to a random access memory IC.
The memory capacity of semiconductor memories has been increased recently. 64K-bit memories are already commercially available, and 256K-bit memories are now being developed and applied in practice. The major problem in the development of large-capacity memories lies in the fact that noise is generated due to increases and variations in bit-line capacitances, thereby resulting in erroneous access. In addition to this disadvantage, power consumption is increased. The present invention has been made to overcome these conventional drawbacks.
FIG. 1 is a circuit diagram showing the main part of a conventional one-transistor type MIS (metal-insulator-semiconductor structure) memory. A pair of bit lines B and B are connected to nodes .circle.a and .circle.b , respectively, of a sense amplifier SA. A word line W0 and a dummy word line DW0 cross the bit line B, and a word line W1 and a dummy word line DW1 cross the bit line B. A memory cell M0 and a dummy cell DM0 are arranged at the intersections of the bit line B and the word line W0 and that of the bit line B and the dummy line DW0, respectively. Similarly, a memory cell M1 and a dummy cell DM1 are arranged at the intersections of the bit line B and the word line W1 and that of the bit line B and the dummy line DW1. It should be noted that only a single word line W0 and W1 is represented for a bit line B or B for illustrative convenience, but in practice a plurality of word lines are provided for each bit line. It should also be noted that the memory cells M0 and M1 and the dummy cells DM0 and DM1 each have the same capacitor C0 and the same selection transistor Q0.
To access the memory cell M0 in the conventional memory, for example, a pulse is simultaneously supplied to the word line W0 and the dummy word line DW1. Small differential readout signals from the memory cell M0 and the dummy cell DM1 appear on the bit lines B and B and are detected and amplified by the sense amplifier SA in response to a latching clock .phi.L in order to determine whether the readout data is set at logic "0" or "1". A voltage applied to the capacitor C0 of the dummy cell DM1 is set by a reference voltage generator Gref at an intermediate level of the voltages corresponding to the data of logic "1" and "0" which are stored in the capacitor C0 of the memory cell M0. Therefore, the voltage appearing on the bit line B upon read access of the dummy cell DM1 has an intermediate level between that of logic "1" and "0". A difference between this intermediate value and the voltages corresponding to the readout data of logic "1" and "0" from the memory cell M0 and appearing on the bit line B become differential signals of opposite polarities.
Since these differential signals are charge-divided by the bit line capacitances, the differential signals corresponding to the differences in stored voltages between a voltage of 5 V (corresponding to the data of "1") and an intermediate voltage of 2.5 V and between a voltage of 0 V (corresponding to the data of "0") and the intermediate voltage of 2.5 V will not be set at .+-.2.5 V. In practice, the differential signals will be about +0.3 V, i.e., about 1/10 of the stored differential voltages of +2.5 V. The differential signal output voltage .DELTA.VB can be approximated as follows: ##EQU1## where VB' and VB' are the voltages at the bit lines B and B after the corresponding word lines W0 and W1 are opened, respectively, and VB is the voltage at the bit line B or B before the corresponding word line W0 or W1 is opened. Further, VS and VS' are the stored voltages at the memory cell M0 and the dummy cell DM1, respectively, before the corresponding word line is opened, and CB is the bit line capacitance which includes the gate capacitance of the memory cell, the diffusion capacitance of the substrate, the input capacitance of the sense amplifier, and the coupling capacitance with other wires. The bit line capacitance CB is generally about 10 times larger than the memory cell capacitance C0 and is the main cause for the decrease in the differential signal output voltages.
A number of bit lines cross each word line. The readout signals from the memory cells appear on the corresponding bit lines. The readout signal on a given bit line causes generation of noise on all other bit lines due to inherent capacitive coupling and capacitive couplings between the bit line and the substrate and between the bit line and the word line. Therefore, the signals on the bit lines B and B are unbalanced. As a result, the possible detection range of the differential signal output voltages is narrowed, and the sense amplifier is erroneously operated.
In the conventional memory shown in FIG. 1, stable operation of the memory is adversely affected by coupling noise associated with the bit line.
In order to solve this problem, a folded bit line type memory is disclosed in U.S. Pat. No. 4,044,340. FIG. 2 is a circuit diagram of this memory cell. The same reference numerals used in FIG. 2 denote the same parts in FIG. 1.
In this improved memory shown in FIG. 2, a pair of bit lines B and B are parallel to each other and are connected at one of the sides of a sense amplifier SA unlike the arrangement of FIG. 1 wherein the bit lines B and B are connected to both sides of the sense amplifier SA, and memory cells and dummy cells are symmetrically arranged at intersections of the bit and word lines.
The noise associated with the inherent capacitive coupling between the bit lines in FIG. 1 can be substantially eliminated. The coupling capacitances between the respective word lines and the corresponding bit lines differ in accordance with the presence/absence of a memory cell. When a given memory cell is accessed, a dummy cell on the side of a nonselected memory cell is accessed to prevent imbalance of the signals read out onto the bit lines B and B.
However, according to both these conventional memories, the bit line is precharged with a power supply voltage VDD, so that power consumption is pretty large.
A conventional low-power consumption memory is disclosed in PCT International Publication No. WO81/03568 wherein the power consumption can be decreased by 50% since the bit lines are precharged with a voltage of VDD/2, and the dummy cells are omitted. FIG. 3 is a circuit diagram of this memory. The same reference numerals used in FIG. 3 denote the same parts in FIGS. 1 and 2.
Assume that a memory cell M0 is selected and data is read out therefrom in the circuit shown in FIG. 3. Since transistors Q10 and Q11 are turned on in response to a clock .phi.P0, bit lines B and B are precharged with an intermediate voltage (to be referred to as VDD/2 although the intermediate voltage slightly differs from VDD/2) between the power supply voltage VDD and the ground potential. When the memory cell M0 is selected and data of logic "1" has been written therein, the voltage at the bit line B increases to an intermediate level between VDD/2 and VDD. However, when data of logic "0" has been written in the memory cell M0, the voltage at the bit line B decreases to an intermediate value between VDD/2 and the ground potential. In the following description, it is assumed that the memory cell M0 stores data of logic "1". When a clock .phi.s goes low, the sense amplifier SA starts to decrease the lower voltage at the bit line B to the ground potential, thereby allowing detection of a difference between voltages at the bit lines B and B. Subsequently, the bit line B is precharged by a pull-up circuit PU to the VDD level, so that data rewriting is performed. The bit lines B and B are held in the floating state, and are connected to be kept at the initial intermediate voltage VDD/2.
According to the circuit shown in FIG. 3, the dummy cells required for the respective bit lines can be omitted. In addition, the precharge voltages at the bit lines become substantially VDD/2. As a result, a densely-packed semiconductor memory on a small chip can be obtained with power consumption substantially 1/2 that of the conventional memory.
However, several problems are still presented by the memory shown in FIG. 3. First, since the dummy cells are omitted, the difference between the capacitances of the bit lines B and B is increased unlike in the conventional arrangement wherein the bit line capacitances are balanced by the combination of the memory and dummy cells. Since no measure is taken against noise generated by a coupling capacitance between the bit line and the word line, erroneous operation may be occurred by the noise. Second, since the capacitances of the pair of bit lines are unbalanced, the sense amplifier cannot be directly coupled to the bit lines. As a result, the bit lines B and B must be connected to the sense amplifier through the transistors Q8 and Q9, respectively. Alternatively, a complex pull-up circuit must be used.